Clock synchronization circuit and semiconductor memory device including clock synchronization circuit
US9245605B2 · kind B2 · utility
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3References
11Claims
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Key dates
| Filing date | Apr 11, 2014 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Apr 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock synchronization circuit includes a delay-locked loop (DLL) and a delay-locked control unit. The DLL is configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal. The delay-locked control unit configured to detect the locked state of the DLL, and to control the DLL based on the determined locked state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.