NAND flash memory array architecture having low read latency and low program disturb
US9245639B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2014 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Oct 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND flash memory achieves low read latency and avoidance of inadvertent programming and program disturb so that the random access and initial page read speeds of the NAND flash memory are generally comparable to that of a NOR flash memory, while preserving the higher memory density and lower power operation characteristics of traditional NAND flash memory relative to NOR flash memory. The reduction in latency is achieved by a NAND memory array architecture which employs a small NAND string, a dual plane interleaved memory architecture, a partitioned NAND array, selectively coupled local bit lines per each global bit line, and a counter-biasing mechanism to avoid inadvertent programming and program disturb.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.