I/O pin capacitance reduction using TSVS
US9245825B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2014 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Jun 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1443
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for reducing pin capacitance and improving off-chip driver performance by using TSVs to enable usage of off-chip drivers located within selected and unselected die of a plurality of stacked die are described. A reduction in pin capacitance allows for faster switching times and/or lower power operation. In some embodiments, a TSV may connect an internal node (e.g., the output of a pre-driver) within a selected die of a plurality of stacked die with the input of an off-chip driver within an unselected die of the plurality of stacked die. In some cases, only a single die within a die stack may be selected (or enabled) at a given time. Using a TSV to connect internal nodes associated with off-chip drivers located within both selected and unselected die of the die stack allows for reduced off-chip driver sizing and thus reduced pin capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.