Method of fabricating a LDMOS device having a first well depth less than a second well depth
US9245997B2 · kind B2 · utility
6Cited by
8References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2014 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Aug 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device capable of increasing a breakdown voltage without an additional epitaxial layer or buried layer with respect to a high-voltage horizontal MOSFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.