Test data reporting during memory testing
US9250992B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Jul 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some implementations, a built-in self-test (BIST) circuitry of a memory device is configured to perform an execution of a test sequence to test the memory device, wherein performing the execution comprises generating addresses of the memory device in accordance with the test sequence and advancing a value of a modulo counter as each of the addresses is generated, enable error logging when a generated address and a value of the modulo counter corresponding to the generated address match an address and a value of the modulo counter stored for a previously detected error, detect an error in data read from the memory device after enabling error logging, and store information associated with the detected error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.