Implementing automated memory address recording in constrained random test generation for verification of processor hardware designs
US9251023B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2013 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Jul 30, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for implementing automated memory address recording in constrained random test generation for verification of processor hardware designs. A test generation program includes a built in feature to keep track of storage addresses used and to make the addresses available to the test definition. This built in feature of a constrained random test generator allows storage addresses used in the past to be accessed by the current instruction generation eliminating the requirement of deliberately establishing target addresses first. This allows separate test events to interact with the same storage addresses without having to write a special test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.