Methods and apparatus for multi-level cache hierarchies
US9251070B2 · kind B2 · utility
1Cited by
2References
18Claims
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Key dates
| Filing date | Dec 19, 2012 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Jun 14, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-level cache structure in accordance with one embodiment includes a first cache structure and a second cache structure. The second cache structure is hierarchically above the first cache. The second cache includes a tag array comprising a plurality of tag entries corresponding to respective addresses of data within a system memory; a selector array associated with the tag array; and a data array configured to store a subset of the data. The selector array is configured to specify, for each corresponding tag entry, whether the data array includes the data corresponding to that tag entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.