Mechanisms for eliminating a race condition between a hypervisor-performed emulation process requiring a translation operation and a concurrent translation table entry invalidation
US9251088B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2013 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Jul 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are computers and methods employing a mechanism for eliminating a race condition between a hypervisor-performed emulation process and a concurrent translation table entry invalidation. Specifically, on a host machine, a hypervisor controls any guest operating systems. In doing so, the hypervisor emulates an instruction by performing a translation operation to acquire a physical address from a virtual address and, if applicable, further from an effective address using translation table(s) (e.g., page tables and, if applicable, segment tables); accesses the physical address; and completes the instruction. During emulation, flagged address table(s) are used to eliminate the race condition. For example, upon receiving an invalidate translation instruction associated with a virtual address, a determination is made as to whether or not the virtual address appears in a flagged virtual address table and, if so, additional action is taken to prevent an error in the translation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.