Patent · US Active

Data compression in processor caches

US9251096B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Sreenivas Subramoney · Bengaluru, IN
Jayesh Gaur · Bengaluru, IN
Alaa R. Alameldeen · Madison, US

Key dates

Filing date	Sep 25, 2013
Grant date	Feb 2, 2016
Priority date	—
Expiry date	Jul 23, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0895
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In an embodiment, a processor includes a cache data array including a plurality of physical ways, each physical way to store a baseline way and a victim way; a cache tag array including a plurality of tag groups, each tag group associated with a particular physical way and including a first tag associated with the baseline way stored in the particular physical way, and a second tag associated with the victim way stored in the particular physical way; and cache control logic to: select a first baseline way based on a replacement policy, select a first victim way based on an available capacity of a first physical way including the first victim way, and move a first data element from the first baseline way to the first victim way. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.