Memory interface signal reduction
US9251874B2 · kind B2 · utility
2Cited by
2References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 21, 2010 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | May 4, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments a controller includes a memory activate pin, one or more combined memory command/address signal pins, and a selection circuit adapted to select in response to the memory activate pin as each of the one or more combined memory command/address signal pins either a memory command signal or a memory address signal. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.