Area-efficient, high-speed, dynamic-circuit-based sensing scheme for dual-rail SRAM memories
US9251889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Oct 9, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a self-timed, dual-rail SRAM includes a self-timing circuit having a logic gate that is powered by voltage VDD and configured to receive a fire-sense-amplifier timing signal and to produce a VDD-domain sense-amplifier-enable signal SOELV. The self-timing circuit includes an inverting level-shifter having complementary N-type and P-type transistors connected in series between voltage VDDA and ground. The N-type transistor's gate is connected to signal SOELV, and both transistors' drain terminals are connected together to produce output signal SOEHVB. The inverting level-shifter also includes two series-connected P-type transistors connected (i) between supply voltage VDDA and the output and (ii) in parallel with the first P-type (pull-up) transistor. An inverter is connected between the output node and the control terminal of one of the series transistors, and the other series-transistor's gate is connected to signal SOELV. Thus, the series transistors provide a rapid latching and latch-breaking function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.