Interconnect arrangement with stress-reducing structure and method of fabricating the same
US9252047B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jan 23, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Feb 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of a semiconductor device structure and a method of fabricating the same are provided. The semiconductor device structure includes a substrate and a first layer formed over the substrate. The semiconductor device structure further includes a stress-reducing structure formed in the first layer, and a portion of the first layer is surrounded by the stress-reducing structure. The semiconductor device structure further includes a conductive feature formed in the portion of the first layer surrounded by the stress-reducing structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.