Method for forming semiconductor layout
US9252115B1 · kind B1 · utility
0Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Jul 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods for an improved semiconductor layout are described herein. Embodiments of the present invention provide a microelectronic device including a microelectronic die and one or more redistribution paths formed thereon for electrically interconnecting at least one bond pad with an exposed portion of the redistribution path. The redistribution paths, bond pads, and exposed portions may be configured to result in the device having a width narrowed by at least the width of the bond pads due to their absence on at least one edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.