Multi-chip package and method of manufacturing the same
US9252123B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Oct 3, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.