Test structure and method for determining overlay accuracy in semiconductor devices using resistance measurement
US9252202B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 23, 2011 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Aug 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/474
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor structures formed by patterning a lower silicon layer. Each includes a zigzag portion with leads at different spatial locations. An upper pattern is formed and includes at least one pattern feature formed over the resistor or resistors. The portions of the resistor or resistors not covered by the upper pattern feature will become silicided during a subsequent silicidation process. Resistance is measured to determine overlay accuracy as the resistor structures are configured such that the resistance of the resistor structure is determined by the degree of silicidation of the resistor structure which is determined by the overlay accuracy between the upper and lower patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.