Gate structure integration scheme for fin field effect transistors
US9252243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Mar 23, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.