Semiconductor device and method of making
US9252271B2 · kind B2 · utility
9Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2013 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Nov 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/018
Abstract
A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.