Phase locked loop and method for generating an oscillator signal
US9252791B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2014 |
| Grant date | Feb 2, 2016 |
| Priority date | — |
| Expiry date | Dec 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) system generates an oscillator signal by providing a fixed control voltage to a programmable voltage to current converter having switch selection inputs and a variable current output. Logic values are provided to the switch selection inputs to adjust a control current at the variable current output and a frequency of the oscillator signal is adjusted based on the control current. The logic values are fixed when a first condition is reached, which is based on the frequency of the oscillator signal, a division factor, and an input reference signal frequency. The fixed control voltage provided to the programmable voltage to current converter is then replaced with a charge pump control voltage based on an error signal. The error signal is based on a comparison of the input reference signal frequency and a fraction of the oscillating frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.