Patent · US Active

Fused multiply-adder with booth-encoding

US9256397B2 · kind B2 · utility

0Cited by
5References
6Claims
0Family size

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Key dates

Filing dateDec 3, 2013
Grant dateFeb 9, 2016
Priority date
Expiry dateJun 24, 2034

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F7/5443
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.