Load latency speculation in an out-of-order computer processor
US9256428B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2013 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Apr 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38585
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Load latency speculation in an out-of-order computer processor, including: issuing a load instruction for execution, wherein the load instruction has a predetermined expected execution latency; issuing a dependent instruction wakeup signal on an instruction wakeup bus, wherein the dependent instruction wakeup signal indicates that the load instruction will be completed upon the expiration of the expected execution latency; determining, upon the expiration of the expected execution latency, whether the load instruction has completed; and responsive to determining that the load instruction has not completed upon the expiration of the expected execution latency, issuing a negative dependent instruction wakeup signal on the instruction wakeup bus, wherein the negative dependent instruction wakeup signal indicates that the load instruction has not completed upon the expiration of the expected execution latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.