Conditional notification mechanism
US9256535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2013 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Dec 10, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The described embodiments comprise a computing device with a first processor core and a second processor core. In some embodiments, during operations, the first processor core receives, from the second processor core, an indication of a memory location and a flag. The first processor core then stores the flag in a first cache line in a cache in the first processor core and stores the indication of the memory location separately in a second cache line in the cache. Upon encountering a predetermined result when evaluating a condition for the indicated memory location, the first processor core updates the flag in the first cache line. Based on the update of the flag, the first processor core causes the second processor core to perform an operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.