Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US9257155B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2014 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Feb 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit further includes voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, and (ii) apply a second voltage to a second group of associated bit lines, and (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.