Multi-port memory cell
US9257172B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2014 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | May 22, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a first data line, a second data line, a reference node, and a memory cell. The reference node is configured to have a reference voltage level corresponding to a first logical value. The memory cell includes a data node, a first transistor and a second transistor connected in series between the first data line and the reference node, and a third transistor between the data node and the second data line. A gate of the first transistor is coupled to the data node, and the first transistor is configured to be turned off when the gate of the first transistor has a voltage level corresponding to the first logical value. The third transistor is configured to be turned off when a gate of the third transistor has a voltage level corresponding to a second logical value different from the first logical value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.