Multi-chip package and method of manufacturing the same
US9257309B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2014 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Apr 18, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion. Thus, the protrusion may not be deflected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.