Semiconductor devices including a stressor in a recess and methods of forming the same
US9257520B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2015 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Apr 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.