Memory architectures having dense layouts
US9257522B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2014 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Sep 29, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments relate to a memory cell to store one or more bits of data. The memory cell includes a capacitor including first and second capacitor plates which are separated from one another by a dielectric. The first capacitor plate corresponds to a doped region disposed in a semiconductor substrate, and the second capacitor plate is a polysilicon or metal layer arranged over the doped region. The memory cell also includes a transistor laterally spaced apart from the capacitor and including a gate electrode arranged between first and second source/drain regions. An interconnect structure is disposed over the semiconductor substrate and couples the gate electrode of the transistor to the second capacitor plate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.