Partial reconfiguration using configuration transaction layer packets
US9257987B1 · kind B1 · utility
6Cited by
5References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 12, 2015 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Jan 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for implementing partial reconfiguration on an integrated circuit (IC) are provided. During runtime, certain configuration changes may be implemented. The embodiments described herein allow for partial reconfiguration updates to be driven via an independent pathway, reducing complex arbitration, freeing additional application memory resources, and enabling customized partial reconfiguration logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.