Patent · US Active

Combined lock/out-of-lock detector for phase locked loops

US9258000B1 · kind B1 · utility

1Cited by

6References

18Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Klemens Kordik · Linz, AT
Thomas Sailer · Metzingen, DE
Rainer Stuhlberger · Puchenau, AT

Key dates

Filing date	Sep 23, 2014
Grant date	Feb 9, 2016
Priority date	—
Expiry date	Sep 23, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/193
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A detector for detecting a locked state and an out-of-lock state of a phase locked loop includes an out-of-lock detector circuit that receives a reference signal and an input signal representing a PLL oscillator signal. The out-of-lock detector detects an out-of-lock state of the PLL and generates an out-of-lock signal indicating whether an out-of-lock state is detected. The detector further includes a lock detector circuit that receives the reference signal and the input signal, detects a locked state of the PLL, and generates a lock signal indicating whether a locked state is detected. A logic circuit receives both the out-of-lock signal and the lock signal and combines both signals to obtain an output signal indicative of whether the PLL is in a locked state or an out-of-lock state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.