Inverse PCP flow remapping for PFC pause frame generation
US9258256B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 2014 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Jul 23, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An overflow threshold value is stored for each of a plurality of virtual channels. A link manager maintains, for each virtual channel, a buffer count. If the buffer count for a virtual channel is detected to exceed the overflow threshold value for a virtual channel whose originating PCP flows were merged, then a PFC (Priority Flow Control) pause frame is generated where multiple ones of the priority class enable bits are set to indicate that multiple PCP flows should be paused. For the particular virtual channel that is overloaded, an Inverse PCP Remap LUT (IPRLUT) circuit performs inverse PCP mapping, including merging and/or reordering mapping, and outputs an indication of each of those PCP flows that is associated with the overloaded virtual channel. Associated physical MAC port circuitry uses this information to generate the PFC pause frame so that the appropriate multiple enable bits are set in the pause frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.