Method for integrated circuit manufacturing
US9262578B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2014 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Aug 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.