Memory having buried digit lines and methods of making the same
US9263095B2 · kind B2 · utility
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10References
23Claims
0Family size
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Key dates
| Filing date | Jul 29, 2013 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Mar 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.