Semiconductor memory device with memory array and dummy memory array
US9263113B2 · kind B2 · utility
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5References
17Claims
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Key dates
| Filing date | Jun 7, 2013 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Jan 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device in which noise is reduced without an increase in chip area. The device is used as an MRAM in which a memory mat is formed on a silicon substrate surface and the central area of the memory mat is used as a memory array and the area around the memory array is used as a dummy memory array. In the dummy memory array, a capacitor is formed between each bit line, each digit line and a supply voltage line, and a grounding voltage line. Therefore the peak value of a current flowing in each of the bit lines, digit lines and supply voltage line is decreased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.