Method of protecting an interlayer dielectric layer and structure formed thereby
US9263252B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2013 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Jan 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.