Combining cut mask lithography and conventional lithography to achieve sub-threshold pattern features
US9263279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2013 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Jul 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12042
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.