Method for forming self-aligned contacts/vias with high corner selectivity
US9263331B2 · kind B2 · utility
1Cited by
3References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 16, 2015 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Jul 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/334
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of etching self-aligned contact/via features in a low-k dielectric layer disposed below a hardmask, which is disposed below a planarization layer. At least one cycle is provided, where each cycle comprises thinning the planarization layer, forming a deposition layer on the hardmask and planarization layer; and etching the low-k dielectric layer masked by the deposition layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.