Methods and materials useful for chip stacking, chip and wafer bonding
US9263416B2 · kind B2 · utility
0Cited by
26References
20Claims
0Family size
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Key dates
| Filing date | Aug 12, 2014 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Aug 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.