Clock cycle compensator and the method thereof
US9264029B2 · kind B2 · utility
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9Claims
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Assignee
Inventor
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Sep 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
One aspect of the present invention is to provide a method for compensating a system duty cycle of a system clock signal. The method in one embodiment comprises the following steps: locking a duty cycle center of the system duty cycle by a delay lock loop; detecting a current system duty cycle of the system clock signal; determining a duty cycle correction amount, wherein the duty cycle correction amount is a gap of the current system duty cycle from a target duty cycle; and changing a polarity of an input reference clock signal according to whether the duty cycle correction amount exceed a threshold amount or not.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.