Implementing dynamic phase error correction method and circuit for phase locked loop (PLL)
US9264052B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2015 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Jan 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/081
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and a circuit for implementing dynamic phase error correction for phase locked loop (PLL) circuits, and a design structure on which the subject circuit resides are provided. The circuit implements dynamic phase error correction and includes an adjustable delay line that is placed in either the reference or feedback clock path. The phase error correction circuit detects the propagation delay of the reference clock path from input pin to the phase frequency detector in the PLL. It also detects the propagation delay of the feedback clock path from input pin to the phase frequency detector in the PLL. The detected propagation delays are compared and a control signal is generated that is proportional to the mismatch. The control signal is applied to the adjustable delay line. The delay of the delay line is continually adjusted until the reference and feedback clock paths are balanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.