Cascode semiconductor device for power factor correction
US9268351B2 · kind B2 · utility
4Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2014 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Apr 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/84
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration: wherein the first field effect transistor is a depletion mode transistor; and wherein the second field effect transistor comprises a first source to gate capacitance and a second additional source to gate capacitance connected in parallel to the first source to gate capacitance. A power factor correction (PFC) circuit comprising the semiconductor device. A power supply comprising the PFC circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.