Maintenance of cache and tags in a translation lookaside buffer
US9268694B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2013 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Sep 26, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB is an additional cache storing collapsed translations derived from the MTLB. Entries in the MTLB, the collapsed TLB, and other caches can be maintained for consistency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.