Memory signal buffers and modules supporting variable access granularity
US9268719B2 · kind B2 · utility
14Cited by
156References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2012 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Sep 1, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described are memory modules that include a configurable signal buffer that manages communication between memory devices and a memory controller. The buffer can be configured to support threading to reduce access granularity, the frequency of row-activation, or both. The buffer can translate controller commands to access information of a specified granularity into subcommands seeking to access information of reduced granularity. The reduced-granularity information can then be combined, as by concatenation, and conveyed to the memory controller as information of the specified granularity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.