Semiconductor device having transistor and semiconductor memory device using the same
US9269413B2 · kind B2 · utility
1Cited by
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21Claims
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Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Jul 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor device capable of preventing off-leakage of the transistor may include a pulse voltage generator configured to generate a pulse voltage, and a transistor configured to have a gate provided with the pulse voltage. The transistor is in an off state in response to the pulse voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.