Apparatus and method for controlling refreshing of data in a DRAM
US9269418B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2012 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Oct 14, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises a dynamic random-access memory (DRAM) for storing data. Refresh control circuitry is provided to control the DRAM to periodically perform a refresh cycle for refreshing the data stored in each memory location of the DRAM. A refresh address sequence generator generates a refresh address sequence of addresses identifying the order in which memory locations of the DRAM are refreshed during the refresh cycle. To deter differential power analysis attacks on secure data stored in the DRAM, the refresh address sequence is generated with the addresses of at least a portion of the memory locations in a random order which varies from refresh cycle to refresh cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.