RRAM memory device and method thereof
US9269428B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 12, 2014 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Jun 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive random-access memory (RRAM) device and a method thereof are disclosed. The RRAM device is contains a plurality of bit cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. Each bit cell includes a transistor and resistive element, the transistor includes a gate, a source and a drain, and the resistive element is coupled to the drain of the transistor. The plurality of word lines are arranged in parallel to one another, and coupled to respective gates of the transistors. The plurality of bit lines are arranged in parallel to one another and being intersected with the plurality of word lines, and coupled to respective drains of the transistors through the resistive elements. The plurality of source lines are arranged in parallel to one another and the plurality of bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.