Semiconductor memory device
US9269445B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 2015 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Mar 1, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a first set of memory cells commonly connected to a first word line, a second set of memory cells commonly connected to a second word line, and a control circuit configured to execute a writing operation on the memory cells, including controlling voltages applied to the first and second word lines. The writing operation includes a coarse program operation and a fine program operation and the control circuit executes the writing operation on the first and second sets of memory cells in a single write operation that includes starting the following operations in order: (1) the coarse program operation on the first set of memory cells; (2) the coarse program operation on the second set of memory cells; (3) the fine program operation on the first set of memory cells; and (4) the fine program operation on the second set of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.