Spacer enabled active isolation for an integrated circuit device
US9269606B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 2014 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Feb 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an active isolation structure in a semiconductor integrated circuit die is disclosed. A first hard mask layer is deposited over a semiconductor substrate. Portions of the first hard mask layer are removed to form at least one trench. A spacer layer is deposited over the first hard mask and extends into each trench to cover exposed portions of the semiconductor substrate surface in each trench. Portions of the spacer layer are removed such that remaining portions define spacer layer walls covering the side walls of each trench. A second hard mask layer is deposited and extends into each trench between opposing spacer layer walls. The spacer layer walls are removed such that remaining portions of the first and second hard mask layers define a mask pattern, which is then transferred to the substrate to form openings in the substrate, which are filled with an isolation material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.