Surface finish on trace for a thermal compression flip chip (TCFC)
US9269681B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2013 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Apr 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/83192
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some implementations provide a semiconductor device that includes a substrate coupled to a die through a thermal compression bonding process. The semiconductor device also includes a trace coupled to the substrate. The trace includes a first conductive material having a first oxidation property. The trace also includes a first surface layer including a second conductive material having a second oxidation property. The second oxidation property is less susceptible to oxidation than the first oxidation property. The first and second conductive materials are configured to provide an electrical path between the die and the substrate. The first surface layer has a thickness that is 0.3 microns (μm) or less.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.