Anti-snapback circuitry for metal oxide semiconductor (MOS) transistor

US9269705B2 · kind B2 · utility

Assignee

• Polar Semiconductor, LLC · US

Inventors

• Kurt Kimber · Minneapolis, US
• David Litfin · Houlton, US

Key dates

• Filing date: May 4, 2012
• Grant date: Feb 23, 2016
• Expiry date: Dec 25, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/819

Abstract

A circuit for protecting a metal oxide semiconductor (MOS) device is configured to hold down or pull down a voltage at a gate of the protected MOS device during an electrostatic discharge (ESD) event. The circuit includes at least one active device or capacitance-providing element connected to the gate of the protected MOS device, configured to pull down or hold down the voltage at the gate of the protected MOS device when the ESD event occurs.