Integrated circuit system with double doped drain transistor
US9269770B2 · kind B2 · utility
0Cited by
18References
20Claims
0Family size
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Key dates
| Filing date | Mar 8, 2007 |
| Grant date | Feb 23, 2016 |
| Priority date | — |
| Expiry date | Nov 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/149
Abstract
An integrated circuit system includes a substrate, forming a gate over the substrate, forming a first drift region having a first counter diffused region and a source diffused region, the first drift region in the substrate adjacent a first side of the gate, and forming a second drift region having a second counter diffused region and a drain diffused region, the second drift region in the substrate adjacent a second side of the gate opposite the first side of the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.