Inventor · Singapore, SG

Francis Benistant

30Patents
6h-index
42Co-inventors
69Inventor score

Filing activity: Apr 8, 1998 → Feb 6, 2018

Most-cited inventions

PatentTitleAreaCited byStatus
US8053340B2 Method for fabricating semiconductor devices with reduced junction diffusion Electricity 97 Active
US9871132B1 Extended drain metal-oxide-semiconductor transistor Electricity 24 Active
US6243289A Dual floating gate programmable read only memory cell structure and method for its fabrication and operation Physics 10 Expired
US6492228B2 Dual floating gate programmable read only memory cell structure and method for its fabrication and operation Physics 10 Expired
US9673084B2 Isolation scheme for high voltage device Electricity 8 Active
US9947788B2 Device with diffusion blocking layer in source/drain region Electricity 7 Active
US8994107B2 Semiconductor devices and methods of forming the semiconductor devices including a retrograde well Electricity 5 Active
US6756268B2 Modified source/drain re-oxidation method and system Electricity 4 Expired
US8354321B2 Method for fabricating semiconductor devices with reduced junction diffusion Electricity 4 Active
US9406752B2 FinFET conformal junction and high EPI surface dopant concentration method and device Electricity 3 Active
US7101743B2 Low cost source drain elevation through poly amorphizing implant technology Electricity 3 Expired
US9966433B2 Multiple-step epitaxial growth S/D regions for NMOS FinFET Electricity 2 Active
US8860142B2 Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction Electricity 2 Active
US6649470B2 Dual floating gate programmable read only memory cell structure and method for its fabrication and operation Physics 2 Expired
US9997225B2 System and method for modular simulation of spin transfer torque magnetic random access memory devices Physics 2 Active
US6972236B2 Semiconductor device layout and channeling implant process Electricity 1 Expired
US7202133B2 Structure and method to form source and drain regions over doped depletion regions Emerging Cross-Sectional Technologies 1 Expired
US9577040B2 FinFET conformal junction and high epi surface dopant concentration method and device Electricity 1 Active
US10164099B2 Device with diffusion blocking layer in source/drain region Electricity 1 Active
US6969646B2 Method of activating polysilicon gate structure dopants after offset spacer deposition Electricity 1 Expired
US9269770B2 Integrated circuit system with double doped drain transistor Electricity 0 Active
US8293544B2 Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction Electricity 0 Active
US7888752B2 Structure and method to form source and drain regions over doped depletion regions Emerging Cross-Sectional Technologies 0 Active
US7037860B2 Modified source/drain re-oxidation method and system Electricity 0 Expired
US7271435B2 Modified source/drain re-oxidation method and system Electricity 0 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.